The present invention is directed to semiconductor integrated circuit devices and, more particularly, to processes for the fabrication of semiconductor integrated circuit devices that include isolation trenches for low leakage transistors.
Various isolation methods have been employed to electrically isolate one or more semiconductor device elements formed in a substrate from other device elements. Such methods have included p-n junction isolation and localized oxidation of silicon (LOCOS). As newer generations of semiconductor device features become increasingly smaller and the number of elements increased, these known methods are often unsuitable or are increasingly difficult to be manufactured in a controllable manner. To isolate such smaller and more highly integrated semiconductor device elements, trench isolation is commonly employed in which a trench is formed in a semiconductor substrate and surrounds the region that is to be electrically isolated and an insulating material is filled in the trench.
A class of ultra-low leakage transistors, known as pass transistors, is widely used in dynamic random access memory (DRAM) arrays for access to the stored charge. With decreasing memory cell size and reduced operating voltage, the stored charge in a cell ranges from about 10,000 to 100,000 elemental electron charges or from about 6 to 60 fC. To retain a large portion of such low charge for a reasonable amount of time (typically hundreds of milliseconds), the leakage current in each cell should be smaller than 10 fA. Various device isolation techniques can influence the leakage current in such ultra-low leakage regime.
To form the isolation trench, one or more etch masking layers are typically deposited on a semiconductor substrate, and then a photoresist film is deposited on the etch masking layer and patterned. Selected regions of the etch masking layer are then removed and expose areas of the semiconductor substrate. The exposed areas of the semiconductor substrate are then etched to a desired depth, and an insulating material is deposited to fill the trench. Any insulating material that is deposited outside of or above the opening of the trench may then be removed. Also, the etch masking material may then be removed or may be removed prior to the deposition of the insulating material.
As the size of semiconductor device features has further decreased, the width of the isolation trenches have likewise decreased. The depth of the isolation trenches is defined by the depth of the various devices formed in the substrate and by the minimum isolation trench perimeter needed to provide effective isolation between the devices. Accordingly, the trench depth may be increased to keep a constant trench perimeter between the devices, for example. The ratio of the trench height to the trench width, known as the aspect ratio, is also increased. Further, three-dimensional (3D) integration of the devices requires even deeper isolation trenches, resulting in even higher aspect ratios. As an example, a DRAM cell may employ a vertical access transistor stacked on top of the storage capacitor. The isolation trench for such a vertical transistor DRAM cell must be deep enough to isolate the lower junction of the vertical pass transistor. For a vertical DRAM cell made with a semiconductor technology employing a 100 nm minimal feature size, for example, the aspect ratio of isolation trenches is approximately 10:1. When an insulating material, such as a high density plasma (HDP) oxide, is deposited in a trench having such an aspect ratio, voids or seams are often formed within the insulating material located in the trench. The voids may be located entirely below the surface of the semiconductor substrate such that the insulating properties of the isolation trench and the insulating material are degraded. Alternatively, the voids may extend above the surface of the semiconductor substrate so that when the device is subsequently planarized, a seam is opened in the insulating material that may be subsequently filled with a polysilicon film or other conducting material that creates shorts between device elements.
It is therefore desirable to provide a trench isolation process wherein the trench is filled with an insulating material in a manner that prevents the formation of voids and seams.
As an alternative, doped oxides such as borophosphosilicate glass (BPSG) may be used to fill the isolation trenches. Because such doped oxides soften and reflow when subjected to high temperatures, the high aspect ratio trenches may be filled with a doped oxide and then subjected to a high temperature anneal that reflows the doped oxide and eliminates the voids and seams that are formed when the doped oxide is deposited in the trench. The use of such doped oxides, however, has the disadvantage that dopants in the oxide, such as boron, arsenic, or phosphorus, may diffuse out of the doped oxide and into the device regions during the anneal step and other subsequent high temperature processing steps and change the characteristics of the devices. Moreover, such doped oxides have the disadvantage of a high etch rate when exposed to wet solvents, such as acids, and thus cannot be etched in a readily controllable or repeatable manner.
Another known alternative is described in U.S. Pat. No. 6,143,626, to Yabu et al. and titled “Method Of Manufacturing A Semiconductor Device Using A Trench Isolation Technique.” A trench is formed in a semiconductor substrate, and an underlying insulating film composed of a high temperature oxide (HTO) film is formed on the substrate. A reflowable film is then deposited with a thickness greater than about one-half of the depth of the trench and is subsequently reflowed by a thermal treatment to eliminate voids. The reflowable film is then etched back so that only a small portion of the film remains at the bottom of the trench. Next, a silicon dioxide film is deposited at a thickness greater than the depth of the trench to form an insulating film that fills the trench. In this scheme, when a doped oxide is used as a reflowable film, the HTO diffusion barrier film must be thick enough to prevent dopant penetration into the device regions. As an example, a typical thermal treatment during transistor fabrication includes high-temperature dopant activation steps conducted at between 950° C.-1050° C. The HTO layer has to be at least 400-600 Å thick to substantially stop any dopant penetration from the oxide into the silicon substrate. Because current state-of-the-art fabrication processes use isolation trenches that are only 100 nm wide, substantial protection from dopant penetration is not practical when the reflowable material is a highly doped oxide. Thus, the process is not suitable for trenches having increasingly smaller feature sizes (of about 120 nm or less) and higher aspect ratios (of about 5 or larger).
Furthermore, the isolation materials and their related deposition processes have specific requirements for use in ultra-low leakage applications such as DRAM arrays. The electrical leakage associated with impurity, structural, and surface defects in the transistor junctions must be minimized to increase its charge retention characteristics. Surface dangling bonds and associated electron traps near the silicon mid-gap energy level at a silicon/isolation trench boundary are typically minimized by growing a high-quality thermal silicon oxide. The thermal oxidation of silicon has been employed in the art for the past thirty years to produce nearly perfect silicon oxide/silicon interface. For a typical thermally grown silicon oxide, the interface density of traps at silicon mid-gap energy is about or less than 1E11 cm−2eV−1 (and typically about 3E10 cm−2eV−1) on a (100) plane of silicon crystal. The surface density of traps at the silicon mid-gap energy level of less than about 5E11 cm−2eV−1 is highly desirable for ultra-low leakage applications.
A known doped oxide, BPSG, exhibits ion gettering property. That is, mobile metal ions (e.g. K+, Na+) diffuse into BPSG layer and quickly chemically bind to phosphorus atoms within the glass matrix. Therefore, a BPSG material located in the vicinity of transistor junction region can adsorb metallic contamination from the junction, thus reducing transistor leakage. The only requirement for efficient ion gettering by BPSG is the ability of ions to diffuse into the BPSG layer. Such a requirement may be satisfied when the mobile ions do not encounter any substantial diffusion barrier between the BPSG layer and the active area of the transistor.
It is therefore desirable to provide trench isolation materials that both avoid the formation of voids and seams as well as are not subject to dopant diffusion and high wet etch rates and reduce transistor off current.